| Specifications |
| Holder Type: |
Differential LVDS Clock Oscillator CXO7050DK2.5;2.5V; Tri-State on pad 1 |
| Frequency: |
100.000000 MHz |
| Frequency Stability at 25°C: |
± 100 ppm |
| Operating Temperature Range: |
± 100 ppm over ±0°C to +70°C (incusive of 25°C tolerance,
±10% input voltage variation, load change, aging, shock and vibration ) |
| Storage Temperature: |
-55°C to +150°C |
| Power Supply Voltage (Vdd): |
+ 2.5V D.C. ± 5% |
| Maximum Supply Current (15pF load): |
16.0 mA |
| Output Swing: |
250 mV min; 350 mV typical; 450 mV max. RL=100Ohm |
| Output Logic Levels: |
High "1" 1.43V typical; 1.6V max, RL=100 ohms.;
Low "0" 0.9V min; 1.1V typical, RL=100 ohms |
| Output Symmetry (Duty Cycle): |
50% ± 5%max. measured at 50% waveform |
| Load: |
RL=100 ohms between output and complimentary output |
| Rise/Fall Time: |
Tr = 0.2 ns. typ; 0.4 ns. max. 20% -> 80% of waveform
Tf = 0.2 ns. typ; 0.4 ns. max. 80% -> 20% of waveform |
| Start Up Time: |
3 ms typical; 10 ms max. |
| Tri-state Function Pin 1: |
If no connection or Vdd *70% min is applied: Output. Internal pull-up
Oscillation disable time is 2µs max.
If Vdd*30% max is applied: High impedance. 10µA typ., enable time 2ms max. |
| Phase Jitter (12 kHz to 20 MHz): |
300 fs typical |
| Phase Noise (125 MHz): |
-60dBc/Hz @ 10Hz, -90dBc/Hz @ 100Hz, -120dBc/Hz @ 1kHz
-136dBc/Hz @ 10kHz, -142dBc/Hz @ 100kHz, -145dBc/Hz @ 1MHz,
-148dBc/Hz @ 10MHz |
| Aging: |
< ±3ppm max. for the first year |
| Reflow Condition: |
260°C max for 10 sec. |
