| Specifications - Product No. G300000000CTCUPN43BA |
| Holder Type: |
Clock Oscillator CXP7050PJF3.3 ; 3.3V(Voltage code is "3.3"); Tri-State on pad 1 |
| Frequency: |
300.000000 MHz |
| Frequency Stability at 25°C: |
± 50.0 ppm |
| Operating Temperature Range: |
± 50.0 ppm -40°C to +85°C |
| Output Logic Levels: |
High "1" Voh Vdd-1.025min., Termination: RL= 50 Ohm to (Vdd-2.0V)
Low "0" VoL Vdd-1.620max., Termination: RL= 50 Ohm to (Vdd-2.0V) |
| Storage Temperature: |
-55°C to +125°C |
| Power Supply Voltage (Vdd): |
+ 3.3V D.C. ± 10% |
| Maximum Supply Current (Differential): |
100.0 mA max. |
| Current with Output Disabled: |
99 mA typical |
| Output Voltage (VOH) (VOL): |
High "1" Vdd-1.165V min, Vdd- 0.8Vmax.
Low "0" Vdd-2.0V min, Vdd- 1.55Vmax.
|
| Tri-state Function Pin 1 (or 2): |
When Pin 1 (or 2) = 1, Output Enable
When Pin 1 (or 2) (at 0.0V), Output High impedance, Disable current: 50µA max. |
| Start Up Time: |
5ms typical;10 ms max. |
| Period Jitter, RMS, peak to peak: |
(decoupling capacitor between Vdd and GND) for 155.520 MHz
RMS: 3ps typ., 5ps max; peak to peak: 20ps typ; 30ps max. |
| Output Symmetry (Duty Cycle): |
50% ± 5%max. (measured at 50% Vdd) |
| Load: |
50 ohms into Vdd -2V or Thevenin equiv.
|
| Input Static Discharge Protection: |
2 kV (min.) |
| Rise (Tr) /Fall Time (Tf): |
0.35ns typical; 0.5ns max. (20%Vdd<->80%Vdd, 15pF load) |
| Phase Jitter: |
0.15 ps typ. (12 kHz to 20 MHz); < 100 fs (1.875 MHz to 20MHz) |
| Phase Noise (156.250 MHz): |
-67dBc/Hz @ 10Hz, -92dBc/Hz @ 100Hz, -112dBc/Hz @ 1kHz
-121dBc/Hz @ 10kHz, -124dBc/Hz @ 100kHz, -136dBc/Hz @ 1MHz,
-153dBc/Hz @ 5MHz |
| Aging: |
< ±2ppm max. for the first year; ±10ppm max.over 10 years |
| Reflow Condition: |
260°C max for 10 sec. |
