| Specifications |
| Holder Type: |
VCXO7050T2.5 Tristate 2..5V (Voltage code is " 2.5 " ) |
| Frequency Range: |
1.000 MHz to 50.0 MHz ( Fun. frequency crystal used ) |
| Initial Freq. Accuracy (at 25 °C): |
To tune to the nominal frequency with Vc = 1.25V ±0.2V |
| Frequency Stability at 25°C/Deviation: |
±25ppm (typ.) , ±50ppm, ±100ppm /±100ppm (typ.), ±150ppm |
| Operating Temperature Range: |
-10°C to +70°C / -40°C to 85°C, Storage Temp. -50°C to +105°C |
| Power Supply Voltage (Vdd): |
+2.5V DC ± 5% |
| Maximum Supply Current: |
15 mA max. |
| Output Load: |
CMOS 15pF (typ.) |
| Output "1" Level (V0H): |
2.25V (min.) CMOS |
| Output "0" Level (V0L): |
0.25V (max.) CMOS |
| Output Symmetry (Duty Cycle): |
40/60% (45/55% optional) |
| Tri-state Function: |
Tri-state Enable High. No connection or Vdd- 0.5Vmin.is applied to a Tri-state pid
to enable output. Ground+0.5Vmax. to disable output (high impedance). |
| Modulation Bandwidth (at -3 dB): |
10KHz min, Vcontrol at 1.65V or at 2.5V |
| Voltage Control: |
1.25V DC Center / 0.25V to 2.25V Range |
| Linearity: |
6% typical; 10% max. |
| Rise/Fall Time TTL: |
6ns (max.) 4ns (typ.) Measured between 0.4V and 2.4V |
| Rise/Fall Time CMOS: |
6ns (max.) 4ns (typ.) Measured between 20% and 80% Vdd
of the wave form (CL = 15pF) |
| Integrated Phase Jitter: |
1 ps max. (12 kHz to 20 MHz) |
| Phase Noise (27MHz at 3.3V): |
-40dBc/Hz at 10Hz offset -147dBc/Hz at 10kHz offset
-104dBc/Hz at 100Hz offset -152dBc/Hz at 100kHz offset
-132dBc/Hz at 1kHz offset -150dBc/Hz at 1MHz offset |
| Start Up Time: |
10 ms (max.), 5ms (typ.) |
| Aging: |
±3 ppm per year (max.) |
| Input Impedance: |
1 M Ohm typical |
| Reflow Condition: |
10 sec. max. at 260°C |
